1. Field of the Invention
The present invention generally relates to boosting circuits, and more particularly to a boosting circuit improved to operate stably in a wider range of power supply voltage. The present invention has particular applicability to a semiconductor memory such as a dynamic random access memory (DRAM) and a static random access memory (SRAM).
2. Description of the Background Art
A boosting circuit is used in various circuits in a semiconductor integrated circuit device for generating a boosted voltage exceeding a predetermined power supply voltage level. For example, a boosting circuit is used in semiconductor memories such as dynamic random access memories and static random access memories for boosting a selected word line to a level higher than the power supply voltage. The present invention is applicable to boosting circuits in various semiconductor integrated circuit devices. In the following, a conventional boosting circuit, and then the problems thereof will be described hereinafter.
FIG. 31 is a circuit diagram of a conventional boosting circuit. Referring to FIG. 31, a boosting circuit includes an NMOS transistor Q21 connected between power supply potential Vcc and an output node N1, and an MOS capacitor C0 connected to output node N1 for boosting. Transistor Q21 has its gate connected to power supply potential Vcc. A parasitic capacitance C21 exists in output node N1. It is assumed that transistor Q21 has a threshold voltage of Vth1.
In operation, output node N1 is precharged to potential Vcc-Vth1 prior to boosting. At the time of boosting, when a clock signal S2 is boosted from ground potential to power supply potential Vcc, the potential V.sub.N1 of output node N1 is boosted as represented in the following equation due to the capacitive coupling of MOS capacitor C0. EQU V.sub.N1 =Vcc-Vth1+{C0/(C0+C21)}.multidot.Vcc (1)
For example, when Vcc=5 volts, Vth1=1 volt, and C0=2.multidot.C21, potential V.sub.N1 becomes approximately 7.3 volts after boosting.
The precharge voltage level of output node N1 must be greater than the threshold voltage Vth0 of MOS capacitor C0 for the boosting circuit of FIG. 31 to operate properly. That is to say, because an inversion layer must be formed below the gate electrode of MOS capacitor C0 prior to boosting, the above condition, i.e. Vcc=Vth1&gt;Vth0 must be satisfied. This condition is represented by the following inequality. EQU Vcc&gt;Vth0+Vth1 (2)
Assuming that Vth0=1.5 volts, and Vth1=1.0 volts, for example, the boosting circuit of FIG. 31 cannot properly operate if the condition of Vcc&gt;2.5 volts is not satisfied. In other words, the boosting circuit of FIG. 3 can operate properly only under the power supply voltage Vcc of not less than 2.5 volts.
FIG. 32 shows the range of power supply voltage Vcc in which the boosting circuit can operate properly. As shown in FIG. 32 (a), the conventional boosting circuit shown in FIG. 31 can operate properly in the range where power supply voltage Vcc is more than approximately 2.5 volts.
The recent trend is towards reduced power supply voltage level under the requirements of higher integration degree and lower power consumption of a semiconductor device. That is to say, the application of a lower power supply voltage to a semiconductor device allows a thinner insulation film such as of MOS transistors and MOS capacitors, resulting in a higher integration density. Also, power consumption can be reduced.
Under such circumstances, a conventional boosting circuit that can properly operate only under the condition of a power supply voltage Vcc greater than 2.5 volts could not be widely applied to a semiconductor device. In other words, the application of a conventional boosting circuit was limited under the trend of a lower power supply voltage due to its small operational margin of the power supply voltage. Furthermore, the reduction (or loss) of the boosted voltage level by threshold voltage Vth1 in the output voltage of the boosting circuit of FIG. 31 was not desired under the requirement of a lower power supply voltage.